1. Technical Field
This invention relates generally to decoupling of voltage planes in printed circuit structures mounting active device structures, such as ASICs and, more particularly, to decoupling voltage planes in printed circuit board structures in which ASICs are mounted, using a discrete capacitor device configured for respective voltage planes within ASIC chip assemblies.
2. Description of the Prior Art
A high current step load, such as may be created by device drivers typically generated within an ASIC (Application Specific Integrated Circuit), acts to create voltage deviations on the power bus due to source impedance of the power bus. As used herein, ASIC means any active device structure, including Bi-Polar, MOS, CMOS, and other similar active device structures, which may sometimes be referred as chip structures or integrated circuit (I/C) chip structures. Ideally, it would be desirable to hold these voltage deviations at zero. However, in the case of core logic and I/O drivers inside of large ASICs, a high di/dt (rate of change of current) load is common. Power distribution to the ASIC loads is by way of power planes within a circuit board to vias (usually several to several dozen), to solder balls, to pins, to ASIC planes, to loads. A typical structure is comprised of a multilayer board, typically in multilayer technology, such as FR-4, to which decoupling capacitors typically in MLC are placed around the ASIC on the board at locations on the circuit board as permitted by the wiring pattern on the surface and vias permitted by inner layer wiring. Normally, there are several dozen to several hundred decoupling capacitors (DCAPS) which are used. However, with this type of arrangement, significant decoupling capacitor parasitic inductance is added to plane distribution inductance to reduce decoupling effectiveness. It is desirable to reduce the parasitic inductances to as low a level as possible.
According to the present invention, a decoupling capacitor structure and its use in a circuit board mounting an ASIC is provided. The capacitor decoupling structure, and preferably the vias in the circuit board and the vias in the ASIC, are arranged in such a way that remote inductance caused by the connection to the decoupling capacitor and the decoupling capacitor itself is significantly reduced. The circuit board and structure are comprised of a printed circuit board having first and second opposite faces and including at least two voltage planes, at least one of which is typically a ground plane, and vias extending from each of the faces to one of the power planes. An ASIC structure is provided having active device(s) thereon and connectors connecting the active devices on the ASIC to the circuit board vias on one face of the printed circuit board. A decoupling capacitor structure is provided which has at least two interlaced conductive plates in a dielectric material forming at least one capacitor. Vias extend from each of the conductive plates through the dielectric material to connect to the circuit board vias on the second face of the printed circuit board or to the ASIC. The vias in the decoupling capacitor structure are configured and arranged such that the vias are parallel to each other and each via connected to one conductive plate is located adjacent a via connected to another conductive plate. This allows the current flowing in adjacent vias to flow in opposite directions and, thus, essentially cancel out any inductive effects generated by the current flowing.
It is also preferred that the vias in the circuit board be configured and arranged in the same manner such that they are parallel to each other and adjacent vias connected to the opposite conductive planes. Moreover, it is preferred, if possible, to design an ASIC chip with any vias therein which are connected to the internal power planes in the ASIC to be configured in the same way as the vias in the circuit board and the vias in the capacitor decoupling structure. It is also preferable that the vias in the ASIC, the vias in the circuit board, and the vias in the decoupling device that are connected to the same step load, be in a straight line through the assembly.